Interconnect arrangement and method for fabricating an interconnect arrangement

ABSTRACT

An interconnect arrangement ( 100 ) has a first layer ( 101 ), a first layer surface ( 102 ), thereon at least two interconnects ( 104 ) having a second layer surface ( 105 ) essentially parallel to the first layer surface ( 102 ), thereon a respective second layer ( 106 ) for each interconnect ( 104 ), the second layers ( 106 ) of adjacent interconnects covering regions between the adjacent interconnects ( 104 ), and thereon a third layer ( 107 ), which completely closes off the regions between the adjacent interconnects ( 104 ) by means of coverage.

[0001] The invention relates to an interconnect arrangement and a methodfor fabricating an interconnect arrangement.

[0002] Integrated circuit arrangements are produced with an ever higherpacking density. The consequence of this is that there is an eversmaller distance between interconnects in metallization planes. Thismeans that there is a rise in capacitances which are formed between theinterconnects and lead to high signal propagation times, a high powerloss and crosstalk. To date, SiO₂ has principally been used asdielectric for insulation between the interconnects; its relativepermittivity ε_(r)=3.9.

[0003] A number of methods for lowering the relative permittivity ε_(r)and thus for lowering the capacitance between interconnects within aninterconnect plane are known, for example from [1], [2], or [3].

[0004] In accordance with the cited prior art, cavities are producedbetween the interconnects within an interconnect plane. The insulatingdielectric which determines the capacitance between the interconnectsthus has a relative permittivity ε_(r) which is almost equal to one. Inthis case, the interconnects themselves are enclosed by solid SiO₂layers at the top and bottom for the purpose of insulation.

[0005] Since the capacitances of the underlying and overlying insulatinglayers also contribute to a not inconsiderable extent to the totalcapacitance between adjacent interconnects within a layer and theseinsulating layers are still composed of solid SiO₂ material, the highrelative permittivity ε_(r) of these insulating layers has aconsiderable influence on the total capacitance between the adjacentinterconnects.

[0006] When using a low-k material for the insulating layer above theinterconnects, the cavities between adjacent interconnects are filledagain owing to the low viscosity of the low-k material. This againresults in a high relative permittivity ε_(r) and thus a high totalcapacitance between adjacent interconnects.

[0007] Consequently, the invention is based on the problem of specifyingan interconnect arrangement and also a method for fabricating aninterconnect arrangement in which the cavities between theinterconnects, irrespective of the material used for the insulatinglayer which covers the interconnects, occupy a largest possible spaceand a smallest possible capacitance is thus achieved between theinterconnects on account of a small relative permittivity ε_(r).

[0008] The problem is solved by means of an interconnect arrangement andalso by means of a method for fabricating an interconnect arrangementhaving the features in accordance with the independent patent claims.

[0009] An interconnect arrangement has a first layer having a firstlayer surface, the first layer having a first insulation material, andat least two interconnects situated on the first layer surface, having asecond layer surface essentially parallel to the first layer surface,the interconnects having a first material which is electricallyconductive. Furthermore, the interconnect arrangement has a second layermade of a second insulation material, which second layer is produced onthe second layer surface of each interconnect and projects beyond theinterconnect, the second layers of adjacent interconnects coveringregions between the adjacent interconnects. Finally, in the interconnectarrangement, a third layer covers the second layers, the third layerhaving a third insulation material and completely closing off theregions between the adjacent interconnects by means of coverage.

[0010] The interconnect arrangement can be designed in such a way thatthe third layer is also arranged in part in the regions between adjacentinterconnects. However, in order to form a largest possible cavitybetween adjacent interconnects, an interconnect arrangement is preferredin which no part of the third layer is arranged in the regions betweenadjacent interconnects.

[0011] In a method for fabricating an interconnect arrangement, at leasttwo interconnects are applied on a first layer surface of a first layer,the interconnects having a second layer surface essentially parallel tothe first layer surface and sidewalls situated between the first layersurface and the second layer surface and also an electrically conductivefirst material and the first layer having a first insulation material.For each interconnect, a second layer made of a first insulationmaterial is produced on the second layer surface, each second layerbeing arranged in such a way that the second layer projects beyond theinterconnect and adjacent second layers are still not touched. Finally,a third layer made of a third insulation material is produced above thesecond layers, as a result of which an interconnect arrangement isformed between the first layer, the adjacent interconnects, the secondlayers and the third layer.

[0012] One advantage of the invention can be seen in the fact that, bymeans of the largest possible cavities as insulating layer betweenadjacent interconnects, the relative permittivity ε_(r) of theinsulating layer between the adjacent interconnects deviates only littlefrom one and the capacitance between these interconnects is thusreduced. The interconnect arrangement enables a considerable reductionin the total capacitance within an integrated circuit. On account ofleakage fields above and below the interconnect arrangement, theeffective relative permittivity ε_(r) for the entire interconnectarrangement is approximately two. In this case, the value of theeffective relative permittivity ε_(r) is dependent on the geometry ofthe entire interconnect arrangement.

[0013] A further advantage of the interconnect arrangement according tothe invention is that the cavities between the interconnects do not haveto be fabricated by means of a selective deposition of a layer ofinsulating material which covers the cavities. Consequently, there isalso no need for time-consuming process optimization for such aselective deposition process. Primarily, the formation of menisci madeof the insulating material in the region of the cavities is avoided onaccount of the invention.

[0014] Preferably, there is a cavity between the first layer, theadjacent interconnects, the second layers and the third layer, whichcavity has an electrically insulating effect between the adjacentinterconnects. This cavity, in which air, vacuum or an insulating gas,for example sulphur hexafluoride (SF₆), is present after completion ofthe interconnect arrangement, thus has a relative permittivity ε_(r) ofalmost equal to one. The interconnect arrangement thus has a smallcapacitance effect.

[0015] In a preferred development of the interconnect arrangementaccording to the invention, at least one intermediate layer made of asecond material is situated between the first layer and theinterconnects. This intermediate layer may be provided for example inorder to provide a barrier for necessary etching processes during thefabrication of the interconnect arrangement, in order that the firstlayer, usually having silicon dioxide (SiO₂), is not damaged.

[0016] The third insulation material is preferably a low-k materialhaving a relative permittivity ε_(r) in the range between 1 and 4. Sincethe third layer, which completely covers the interconnect arrangementand effects insulating screening in the vertical direction with respectto the first layer surface, also makes a contribution to the totalcapacitance between adjacent interconnects, care should be taken toensure that the third insulation material used for the third layer alsohas a low relative permittivity ε_(r).

[0017] In a preferred development of the interconnect arrangementaccording to the invention, the third insulation material is a low-kmaterial having a relative permittivity ε_(r) in the range between 1.5and 3.

[0018] The second insulation material and/or the third insulationmaterial of the interconnect arrangement preferably have silicon dioxide(SiO₂). As an alternative, the second insulation material and/or thethird insulation material may also have silicon nitride (Si₃N₄) or anorganic material. Furthermore, a silicon-based oxide-nitride may also beused as second insulation material and/or as third insulation material.In order to obtain a low relative permittivity ε_(r) when using theseinsulation materials, the respective insulation material should beapplied in porous form. When using organic material, polymers arepreferably applied in a methane environment during a PECVD process(PECVD=plasma enhanced chemical vapour deposition).

[0019] In a preferred development of the interconnect arrangementaccording to the invention, the first layer has at least two partiallayers arranged one above the other, the upper partial layer beingpatterned in accordance with the regions between the interconnects insuch a way that the upper partial layer is arranged below theinterconnects and is at least partly absent below the regions betweenthe interconnects. Consequently, between adjacent interconnects,trenches are formed in the insulating first layer. This arrangement hasthe advantage that the interconnects are not applied directly on aninsulation layer which connects the interconnects over the shortestroute. An insulation layer which connects the interconnects over theshortest route promotes electrical leakage fields between adjacentinterconnects. This results in an unsatisfactory value for the effectiverelative permittivity ε_(r) and thus for the total capacitance betweenadjacent interconnects. A patterned upper partial layer makes itpossible to enlarge the connecting route between adjacent interconnectsand thus to further reduce the effective relative permittivity ε_(r). Apatterned upper partial layer thus enables a further reduction in thetotal capacitance between adjacent interconnects.

[0020] If the two partial layers have the same insulation material, anetching stop layer made of a third material is preferably situatedbetween the upper partial layer and the lower partial layer. In thiscase, the third material is preferably essentially resistant to etchantwhich acts on the first insulation material. Consequently, thepatterning of the upper partial layer can be fabricated by etching theupper partial layer with the interconnects as mask. The etching is endedwhen the etching stop layer is uncovered below the regions betweenadjacent interconnects. Consequently, the depth of the trenches betweenadjacent interconnects can be set by means of the thickness of the upperpartial layer.

[0021] In a method for fabricating an interconnect arrangement, beforethe application of the interconnects on the first layer surface,preferably at least one intermediate layer made of a second material isproduced on the first layer surface. The intermediate layer is providedas a barrier for etching processes during the fabrication of theinterconnect arrangement, in order that the first layer, usually havingsilicon dioxide (SiO₂) is not damaged. If an oxygen compound is chosenas first insulation material for the first layer, then a nitrogencompound, for example a titanium-nitrogen compound, is preferably usedas second material for the intermediate layer. If a titanium-nitrogencompound is used, the intermediate layer must also be removed on regionsof the first layer surface which are not covered by the interconnects.This is usually achieved by means of an etching process, theinterconnects serving as mask for the intermediate layer. When using anitrogen compound as first insulation material for the first layer, anoxygen compound is preferred as second material for the intermediatelayer. If the same material is used for the intermediate layer and alsofor the subsequently fabricated spacers, then a thin, furtherintermediate layer made of a different material is preferably provideddirectly above the intermediate layer.

[0022] Preferably, trenches which reach at least partly into the firstlayer are produced between adjacent interconnects. This lengthens theconnecting route between adjacent interconnects and reduces theproduction of electrical leakage fields which adversely affect the totalcapacitance.

[0023] The first layer is preferably produced from an upper partiallayer, an etching stop layer and a lower partial layer. The trenchesbetween adjacent interconnects are then produced by the fact that, usingthe interconnects as mask, the upper partial layer is removed below theregions between adjacent interconnects. The etching stop layer isuncovered in the process. If silicon dioxide (SiO₂) is chosen as firstinsulation material for the first layer and thus for the upper partiallayer and also for the lower partial layer, then silicon nitride(Si₃N₄), for example, can be used for the etching stop layer.

[0024] In a preferred development of the method according to theinvention, spacers are produced on the sidewalls of the interconnects,the spacers having a spacer material and being arranged in such a waythat spacers of adjacent interconnects still do not touch one another.In this case, the spacers serve as auxiliary supports for thefabrication of the second layers, which project beyond theinterconnects. The spacer material used is preferably silicon nitride(Si₃N₄) which is applied conformally to the sidewalls of theinterconnects. As an alternative, it is also possible to use anotherspacer material which can be applied conformally and etched selectivelywith respect to the second layers and also with respect to the firstlayer.

[0025] In a preferred embodiment of the method according to theinvention, the spacers are produced on the sidewalls of theinterconnects by means of a conformal deposition of spacer material andselective and anisotropic etching of the spacer material. Firstly,spacer material is deposited conformally over the interconnects and overregions of the first layer surface which are not covered by theinterconnects. The spacer material is subsequently etchedanisotropically and selectively parallel to the second layer surface.This enables targeted fabrication and setting of the form of thespacers. The thickness of the deposited spacer material is preferablyset in such a way that the remaining gap between two adjacentinterconnects is only just not closed. Consequently, a thin air gapremains between the adjacent interconnects or the spacers situated onthe sidewalls thereof.

[0026] In the method according to the invention, the spacers arepreferably removed again below the second layers. Since the spacers onlyserve as auxiliary supports for the fabrication of the second layers andwould obstruct formation of the largest possible cavities between theinterconnects, the spacers are removed again after the fabrication ofthe second layers.

[0027] The second layers are preferably produced by means of anon-conformal method essentially parallel to the first layer surfaceabove the second layer surface and the spacers. To that end, the secondinsulation material of the second layers is deposited by means of a CVDprocess (CVD=chemical vapour deposition) with the smallest possible edgecoverage principally on the interconnects which are widened by thespacers. To that end, the CVD process is operated in thediffusion-determined regime, preferably by means of increasing thepressure. Instead of using a CVD process, it is also possible tofabricate the second insulation material for fabricating the secondlayers by means of a sputtering process. A second insulation materialthat has possibly penetrated deeply into the air gaps can be removedagain with the aid of a short isotropic etching, for examplewet-chemically or else in dry fashion in a downstream etching process.Such a downstream etching process is described in [4].

[0028] In a preferred embodiment of the method according to theinvention, the spacer material of the spacers is etched away after theproduction of the second layers, a selective etching process beingemployed. In this case, the selective etching process is preferablyisotropic. In this case, the air gap situated between adjacent spacersis necessary for the removal of the spacers in order to offer theetchant an area of attack on the spacers. Possible etching processesare, for example, a wet-chemical etching process or a downstreamdry-etching process, described in [5] for a silicon dioxide (SiO₂), withhigh selectivity.

[0029] The third layer is preferably produced in such a way that firstlythird insulation material is deposited by means of a non-conformalmethod over the second layers until cavities have formed between thefirst layer, the adjacent interconnects, the second layers and the thirdlayer. Afterwards, third insulation material is deposited by means of aconformal standard method. During the non-conformal method, hardly anythird insulation material penetrates into the resulting cavities owingto the second layers acting in a screen-like manner. As a result, thesidewalls of the interconnects are covered with third insulationmaterial only to a very small extent, as a result of which the relativepermittivity ε_(r) of the entire interconnect arrangement is influencedonly to an insignificant extent. In the case of relatively small featuresizes such as, for example, of a very large scale integrated circuit(VLSI circuit=very large scale integration), it is not possible toascertain any coverage of the sidewalls of the interconnects with thirdinsulation material.

[0030] Exemplary embodiments of the invention are illustrated in thefigures and are explained in more detail below. In this case, identicalreference symbols designate identical components.

[0031] In the figures:

[0032]FIG. 1 shows a cross section through an interconnect arrangementin accordance with a first exemplary embodiment of the invention;

[0033]FIG. 2 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a first timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

[0034]FIG. 3 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a second timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

[0035]FIG. 4 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a third timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention;

[0036]FIG. 5 shows a cross section through an as yet not completedinterconnect arrangement in accordance with FIG. 1 at a fourth timeduring the performance of the fabrication method in accordance with thefirst exemplary embodiment of the invention; and

[0037]FIG. 6 shows a cross section through an as yet not completedinterconnect arrangement at a first time during the performance of thefabrication method in accordance with a second exemplary embodiment ofthe invention.

[0038]FIG. 1 shows a cross section through an interconnect arrangement100 in accordance with a first exemplary embodiment of the invention.

[0039] The interconnect arrangement 100 has a substrate having asubstrate surface formed as first layer surface 102 as first layer 101.An insulating material, silicon dioxide (SiO₂) in accordance with thisexemplary embodiment, is chosen as substrate material.

[0040] Situated on the first layer surface 102 are interconnects 104made of aluminium or copper with a respective intermediate layer 103made of a titanium-nitrogen compound between the first layer surface 102and the interconnects 104. The interconnects 104 are bounded by a secondlayer surface 105 arranged parallel to the first layer surface 102 andalso sidewalls 108 which connect the first layer surface 102 and thesecond layer surface 105.

[0041] Situated on the second layer surface 105 of each interconnect 104is a second layer 106 made of silicon dioxide (SiO₂), which projectsbeyond the respective interconnect 104. In this exemplary embodiment ofthe invention, the second layers 106 have the form of screens coveringthe interconnects 104. In this case, the second layers 106 cover regionsbetween adjacent interconnects 104. Since the second layers 106 ofadjacent interconnects 104 do not touch one another, the regions betweenthe adjacent interconnects 104 are not completely closed off by thesecond layers 106.

[0042] A third layer 107 made of silicon dioxide (SiO₂) covers thesecond layers 106 and thus completely closes off the regions between theadjacent interconnects 104. Consequently, cavities 109 enclosed by thefirst layer surface 102, the sidewalls 108 of the interconnects 104, thesecond layers 106 and the third layer 107 are situated between adjacentinterconnects 104.

[0043] During the fabrication of the third layer 107, silicon dioxide(SiO₂) was able to penetrate into the incompletely closed-off regionsbetween the adjacent interconnects 104. This caused a thin covering 110of the sidewalls 108 of the interconnects 104 and also of that part ofthe first layer surface 102 not covered by the interconnects 104 withsilicon dioxide (SiO₂). The smaller the distance between adjacent secondlayers 106, the smaller the covering 110 of the sidewalls 108 of theinterconnects 104 and also of that part of the first layer surface 102not covered by the interconnects 104. In another exemplary embodiment ofthe invention (not illustrated in the figures), the second layers 106can also be fabricated with such a small spacing that no covering 110whatsoever is produced.

[0044] At the end of the interconnect arrangement 100, the lastinterconnect 104 has an adjacent interconnect 104 only on one side. Onthe side without an adjacent interconnect 104, the last interconnect 104requires electrical insulation from the environment. In this case, it ispossible to dispense with a low relative permittivity ε_(r) for lack ofa further electrically conductive element representing a capacitance.Consequently, the last interconnect 104 is not electrically insulated bymeans of a cavity 109 like between adjacent interconnects 104, but bymeans of a terminating cavity 111 and a terminating insulating layer112.

[0045] The distance between adjacent interconnects 104 and the thicknessof the interconnects 104 should preferably be chosen in such a way thatthe interconnect arrangement 100 has a sufficiently good carryingcapability for further layers and metallization planes arranged abovethe interconnect arrangement 100. In accordance with this exemplaryembodiment, the interconnects 104 each have a width which is almostequal to the distance between adjacent interconnects 104. In accordancewith this exemplary embodiment, the interconnects 104 have a heightcorresponding to twice the width of the interconnects 104.

[0046] As an alternative, it is also possible to choose other dimensionsfor the width, the height and/or the spacings of the interconnects 104.

[0047] A method for forming the interconnect arrangement 100 inaccordance with the first exemplary embodiment of the invention isdescribed step by step below.

[0048]FIG. 2 shows a cross section through an as yet not completedinterconnect arrangement 200 at a first time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

[0049] A substrate having a substrate surface formed as first layersurface 102 is used as first layer 101. The substrate material issilicon dioxide (SiO₂). An intermediate layer 103 made of atitanium-nitrogen compound is applied over the area of the first layersurface 102 using a conventional standard method. If the interconnectmaterial is aluminium, the intermediate layer 103 serves as adhesionlayer for the interconnects 104 on the first layer 101, and if theinterconnect material is copper, the said intermediate layer serves as abarrier against copper diffusion in order to protect the first layer101. If the interconnect material is copper, the intermediate layer 103may also have tantalum or a tantalum-nitrogen compound.

[0050] A plurality of interconnects 104 made of aluminium or copper areformed above the intermediate layer 103 using known subtractive methods.The interconnects 104 terminate with a second layer surface 105 parallelto the first layer surface 102 and have sidewalls 108 which connect thesecond layer surface 105 and the first layer surface 102.

[0051] During the fabrication of interconnects 104 made of copper, theso-called damascene technique may preferably be employed: firstly anauxiliary layer made of silicon dioxide (SiO₂) is applied on the area ofthe first layer surface 102 covered by the intermediate layer 103. Inthis case, the thickness of this auxiliary layer is set in accordancewith the desired height for the interconnects 104 to be fabricated.Using customary lithography and etching techniques, trenches are etchedinto the said auxiliary layer at the locations at which theinterconnects 104 are intended to be formed. These trenches have thedesired width and the desired distance from one another in accordancewith the interconnects 104 to be fabricated and reach down to theintermediate layer 103.

[0052] A barrier layer made, for example, of a tantalum-nitrogencompound and then copper are then deposited over the auxiliary layerwith the trenches by means of customary metallization methods, thetrenches being overfilled. In order to fabricate the second layersurface 105 parallel to the first layer surface 102, the copperoverfilling the trenches and also the barrier layer are removed areallyby means of chemical mechanical polishing. Finally, the auxiliary layermade of silicon dioxide (SiO₂) is removed selectively with respect tocopper by means of etching until the intermediate layer 103 is reached.The intermediate layer 103 made of a titanium-nitrogen compound acts asan etching stop layer in this case. The interconnects 104 formed on thefirst layer surface 102 and the intermediate layer 103 remain.

[0053] The process for fabricating the interconnects 104 also includesthe final etching of the intermediate layer 103 at all the locationswhich are not covered by the interconnects 104. In this case, theinterconnects 104 serve as mask for the final etching. As a result, thefirst layer surface 102 is uncovered again between the interconnects104. Consequently, the intermediate layer 103 is now situatedexclusively between the interconnects 104 and the first layer surface102.

[0054]FIG. 3 shows a cross section through an as yet not completedcavity structure 300 at a second time during the performance of thefabrication method in accordance with the first exemplary embodiment ofthe invention.

[0055] Spacers 301 made of silicon nitride (Si₃N₄) are produced on thesidewalls 108 of the interconnects 104 conformally by means of conformaldeposition and subsequent etching, the spacers 301 being arranged insuch a way that spacers 301 of adjacent interconnects 104 still do nottouch one another. In this case, the spacers 301 serve as auxiliarysupports for the subsequent fabrication of the second layers 106 whichproject beyond the interconnects 104.

[0056] The selective and anisotropic etching of the conformallydeposited spacer material enables targeted fabrication and setting ofthe form of the spacers 301. The thickness of the deposited spacermaterial is preferably set in such a way that the remaining gap betweentwo adjacent interconnects 104 is only just not closed. Consequently, athin air gap 302 remains between the adjacent interconnects 104 or thespacers 301 situated on the sidewalls 108 thereof.

[0057]FIG. 4 shows a cross section through an as yet not completedinterconnect arrangement 400 at a third time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

[0058] The second layers 106 made of silicon dioxide (SiO₂) are producedby a non-conformal method essentially parallel to the first layersurface 102 above the second layer surface 105 and the spacers 301. Tothat end, the silicon dioxide (SiO₂) is deposited by means of a CVDprocess with as little edge coverage as possible principally on theinterconnects 104 widened by the spacers 301. To that end, the CVDprocess is operated in the diffusion-determined regime by means ofincreasing the pressure. Silicon dioxide (SiO₂) that has possiblypenetrated deeply into the air gaps 302 is removed again by means of ashort isotropic etching in a downstream etching process.

[0059]FIG. 5 shows a cross section through an as yet not completedinterconnect arrangement 500 at a fourth time during the performance ofthe fabrication method in accordance with the first exemplary embodimentof the invention.

[0060] Since the spacers 301 clearly essentially serve as auxiliarysupports for the fabrication of the second layers 106 and obstructformation of the largest possible cavities 109 between the interconnects104, the spacers 301 are removed again after the fabrication of thesecond layers 106. To that end, the silicon nitride (Si₃N₄) of thespacers 301 is etched away after the production of the second layers106, a selective, isotropic etching process being employed. In thiscase, the air gap 302 situated between adjacent spacers 301 is necessaryfor the removal of the spacers 301 in order to offer the etchant an areaof attack in the spacers 301.

[0061] The largest possible interspaces 502 are now situated between thesidewalls 108 of adjacent interconnects 104, the first layer surface 102and the second layers 106. On account of the distance between them,respectively adjacent second layers 106 form openings 501 for theinterspaces 502, as a result of which the interspaces 502 are notcompletely closed off.

[0062] In order to form cavities 109 from the interspaces 502, theopenings 501 must now be closed. Therefore, the third layer 107 isproduced in two separate method steps. Firstly, silicon dioxide (SiO₂)is deposited by means of a non-conformal method over the second layers106 until the openings 501 are closed and cavities 109 have formedbetween the first layer 101, the adjacent interconnects 104, the secondlayers 106 and the third layer 107. Afterwards, silicon dioxide (SiO₂)is deposited by means of a conformal standard method in order to form athick insulating third layer 107, as is illustrated in FIG. 1.

[0063] During the non-conformal method, hardly any silicon dioxide(SiO₂) penetrates into the resulting cavities 109 owing to the secondlayers 106 acting in a screen-like manner. As a result, only a verysmall covering 110 of the sidewalls 108 of the interconnects 104 withsilicon dioxide (SiO₂) is produced, as a result of which the relativepermittivity ε_(r) of the entire interconnect arrangement 100 isinfluenced only to an insignificant extent.

[0064] The interconnect arrangement 100, and thus also a lastinterconnect 104 without an adjacent interconnect 104 beside one of itstwo sidewalls 108, requires electrical insulation from the environment.Therefore, the third layer 107 is formed above the entire interconnectarrangement 100. Since the last interconnect 104 has an adjacentinterconnect 104 only beside one of its two sidewalls 108, the lastinterconnect 104 is not electrically insulated by means of a cavity 109like between adjacent interconnects 104 but by means of a terminatingcavity 111 and a terminating insulation layer 112. In this case, theterminating insulation layer 112 is produced as a side effect during theproduction of the third layer 107 and thus likewise has silicon dioxide(SiO₂).

[0065]FIG. 6 shows a cross section through an as yet not completedinterconnect arrangement 600 at a first time during the performance ofthe fabrication method in accordance with a second exemplary embodimentof the invention.

[0066] The as yet not completed interconnect arrangement 600 of thesecond exemplary embodiment differs from the as yet not completedinterconnect arrangement 200 of the first exemplary embodiment only inthe different structure of the first layer 101.

[0067] In accordance with this exemplary embodiment, the first layer 101has an upper partial layer 601 made of silicon dioxide (SiO₂), anetching stop layer 602 made of silicon. nitride (Si₃N₄) and a lowerpartial layer 603 made of silicon dioxide (SiO₂). However, the firstlayer 101 may also be composed of layers with different insulationmaterials. If different insulation materials with a different behaviourduring an etching process are used for the upper partial layer 601 andthe lower partial layer 603, it is possible to dispense with the etchingstop layer 602.

[0068] The upper partial layer 601 is patterned in such a way that it isarranged below the interconnects 104 and is missing below the regionsbetween the interconnects 104. Situated in the upper partial layer 601are trenches 604 which reach down with uniform width between theinterconnects 104 from the second layer surface 105 as far as theetching stop layer 602.

[0069] The upper partial layer 601 can be patterned as follows: firstly,the silicon dioxide (SiO₂) for the upper partial layer 601 is depositedareally. Afterwards, the interconnects 104 are fabricated, as alreadyexplained in the description with respect to FIG. 2. The trenches 604are subsequently etched into the areally deposited insulation material,the interconnects being used as an etching mask. In this case, by way ofexample, a wet-chemical downstream etching process may be employed. Inthe selection of the etching process to be employed, care should betaken to ensure that the etchant preferably acts on the silicon dioxide(SiO₂), and not on the interconnect material. The etching process isended as soon as the etching stop layer 602 is uncovered.

[0070] In accordance with this exemplary embodiment, the trenches 604have a depth which preferably corresponds to 0.5 to 2 times the width ofthe interconnects 104.

[0071] The further fabrication steps for an interconnect arrangement inaccordance with the second exemplary embodiment correspond to thefabrication steps described above for the first exemplary embodiment.The interconnect arrangement in accordance with the second exemplaryembodiment thus essentially corresponds to the interconnect arrangement100 in accordance with the first exemplary embodiment. The two exemplaryembodiments differ merely in the construction of the first layer 101.Thus, the cavities 109 in the second exemplary embodiment have, comparedwith the first exemplary embodiment, a larger volume owing to theexistence of the trenches 604.

[0072] To form an interconnect arrangement according to the invention inaccordance with the first or second exemplary embodiment, instead of thechosen insulation materials and the fabrication processes thereof, it isalso possible to use other insulating materials and fabricationprocesses.

[0073] By way of example, what are suitable as third insulation materialfor the third layer 107 are insulating low-k materials having a lowrelative permittivity ε_(r) which are applied in a spin-on process andhave a low viscosity. In a spin-on process, the usually liquid materialto be applied is applied to the areas to be coated during spin-coatingby means of spin-on.

[0074] If a low-k material having high viscosity is used as thirdinsulation material and, as a result, no third insulation materialpenetrates through the openings 501 into the interspaces 502, and so nocovering 110 is thus produced, the low-k material can be used directlyto terminate the cavities 109 and thus to form the third layer 107.Otherwise, firstly silicon dioxide (SiO₂) for terminating the cavities109 is deposited non-conformally over the openings 501 and only then isthe low-k material deposited as third layer 107.

1. Interconnect arrangement having a first layer and a first layersurface, the first layer having a first insulation material, having atleast two interconnects situated on the first layer surface, having asecond layer surface essentially parallel to the first layer surface,the interconnects having a first material which is electricallyconductive, having a second layer made of a second insulation material,which second layer is produced on the second layer surface of eachinterconnect and projects beyond the interconnect, the second layers ofadjacent interconnects covering regions between the adjacentinterconnects, and having a third layer covering the second layers, thethird layer having a third insulation material and completely closingoff the regions between the adjacent interconnects by means of coverage.2. Interconnect arrangement according to claim 1, in which the thirdlayer is also arranged in part in the regions between adjacentinterconnects.
 3. Interconnect arrangement according to claim 1 or 2, inwhich there is a cavity between the first layer, the adjacentinterconnects, the second layers and the third layer, which cavity hasan electrically insulating effect between the adjacent interconnects. 4.Interconnect arrangement according to one of claims 1 to 3, in which atleast one intermediate layer made of a second material is situatedbetween the first layer and the interconnects.
 5. Interconnectarrangement according to one of claims 1 to 4, in which the thirdinsulation material is a low-k material having a relative permittivityε_(r) in the range between 1 and
 4. 6. Interconnect arrangementaccording to one of claims 1 to 5, in which the third insulationmaterial is a low-k material having a relative permittivity ε_(r) in therange between 1.5 and
 3. 7. Interconnect arrangement according to one ofclaims 1 to 6, in which the second insulation material and/or the thirdinsulation material have silicon dioxide.
 8. Interconnect arrangementaccording to one of claims 1 to 7, in which the second insulationmaterial and/or the third insulation material have silicon nitride. 9.Interconnect arrangement according to one of claims 1 to 8, in which thesecond insulation material and/or the third insulation material have anorganic material.
 10. Interconnect arrangement according to one ofclaims 1 to 9, in which the first layer has at least two partial layersarranged one above the other, the upper partial layer being patterned inaccordance with the regions between the interconnects in such a way thatthe upper partial layer is arranged below the interconnects and is atleast partly absent below the regions between the interconnects. 11.Interconnect arrangement according to claim 10, in which the two partiallayers have the same first insulation material and an etching stop layermade of a third material is situated between the upper partial layer andthe lower partial layer, the third material essentially being resistantto the etchant acting on the first insulation material.
 12. Method forfabricating an interconnect arrangement, in which at least twointerconnects are applied on a first layer surface of a first layer, theinterconnects having a second layer surface essentially parallel to thefirst layer surface and sidewalls situated between the first layersurface and the second layer surface and also an electrically conductivefirst material and the first layer having a first insulation material,in which, for each interconnect, a second layer made of a firstinsulation material is produced on the second layer surface, each secondlayer being arranged in such a way that the second layer projects beyondthe interconnect and adjacent second layers are still not touched, andin which a third layer made of a third insulation material is producedabove the second layers, as a result of which an interconnectarrangement is formed between the first layer, the adjacentinterconnects, the second layers and the third layer.
 13. Methodaccording to claim 12, in which, before the application of theinterconnects on the first layer surface, at least one intermediatelayer made of a second material is produced on the first layer surface.14. Method according to claim 12 or 13, in which trenches which reach atleast partly into the first layer are produced between adjacentinterconnects.
 15. Method according to claim 14, in which the firstlayer is produced from an upper partial layer, an etching stop layer anda lower partial layer, and in which the trenches are produced betweenadjacent interconnects by the fact that, using the interconnects asmask, the upper partial layer is removed below the regions betweenadjacent interconnects and the etching stop layer is uncovered. 16.Method according to one of claims 12 to 15, in which spacers areproduced on the sidewalls of the interconnects, the spacers having aspacer material and being arranged in such a way that spacers ofadjacent interconnects still do not touch one another.
 17. Methodaccording to claim 16, in which the spacer material is firstly depositedconformally and then etched anisotropically and selectively parallel tothe first layer surface.
 18. Method according to claim 16 or 17, inwhich the spacers are removed again below the second layers.
 19. Methodaccording to one of claims 16 to 18, in which the second layers areproduced by means of a non-conformal method essentially parallel to thefirst layer surface above the second layer surface and the spacers. 20.Method according to one of claims 16 to 19, in which the spacer materialof the spacers is etched away after the production of the second layers,a selective etching process being employed.
 21. Method according toclaim 20, in which the selective etching process is isotropic. 22.Method according to one of claims 12 to 21, in which the third layer isproduced in such a way that firstly third insulation material isdeposited by means of a non-conformal method over the second layersuntil cavities have formed between the first layer, the adjacentinterconnects, the second layers and the third layer, and thirdinsulation material is subsequently deposited by means of a conformalstandard method.